jfdctint-avx2.asm 12 KB

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  1. ;
  2. ; Accurate integer FDCT (64-bit AVX2)
  3. ;
  4. ; Copyright 2009 Pierre Ossman <ossman@cendio.se> for Cendio AB
  5. ; Copyright (C) 2009, 2016, 2018, 2020, 2024, D. R. Commander.
  6. ;
  7. ; Based on the x86 SIMD extension for IJG JPEG library
  8. ; Copyright (C) 1999-2006, MIYASAKA Masaru.
  9. ; For conditions of distribution and use, see copyright notice in jsimdext.inc
  10. ;
  11. ; This file should be assembled with NASM (Netwide Assembler) or Yasm.
  12. ;
  13. ; This file contains a slower but more accurate integer implementation of the
  14. ; forward DCT (Discrete Cosine Transform). The following code is based
  15. ; directly on the IJG's original jfdctint.c; see the jfdctint.c for
  16. ; more details.
  17. %include "jsimdext.inc"
  18. %include "jdct.inc"
  19. ; --------------------------------------------------------------------------
  20. %define CONST_BITS 13
  21. %define PASS1_BITS 2
  22. %define DESCALE_P1 (CONST_BITS - PASS1_BITS)
  23. %define DESCALE_P2 (CONST_BITS + PASS1_BITS)
  24. %if CONST_BITS == 13
  25. F_0_298 equ 2446 ; FIX(0.298631336)
  26. F_0_390 equ 3196 ; FIX(0.390180644)
  27. F_0_541 equ 4433 ; FIX(0.541196100)
  28. F_0_765 equ 6270 ; FIX(0.765366865)
  29. F_0_899 equ 7373 ; FIX(0.899976223)
  30. F_1_175 equ 9633 ; FIX(1.175875602)
  31. F_1_501 equ 12299 ; FIX(1.501321110)
  32. F_1_847 equ 15137 ; FIX(1.847759065)
  33. F_1_961 equ 16069 ; FIX(1.961570560)
  34. F_2_053 equ 16819 ; FIX(2.053119869)
  35. F_2_562 equ 20995 ; FIX(2.562915447)
  36. F_3_072 equ 25172 ; FIX(3.072711026)
  37. %else
  38. ; NASM cannot do compile-time arithmetic on floating-point constants.
  39. %define DESCALE(x, n) (((x) + (1 << ((n) - 1))) >> (n))
  40. F_0_298 equ DESCALE( 320652955, 30 - CONST_BITS) ; FIX(0.298631336)
  41. F_0_390 equ DESCALE( 418953276, 30 - CONST_BITS) ; FIX(0.390180644)
  42. F_0_541 equ DESCALE( 581104887, 30 - CONST_BITS) ; FIX(0.541196100)
  43. F_0_765 equ DESCALE( 821806413, 30 - CONST_BITS) ; FIX(0.765366865)
  44. F_0_899 equ DESCALE( 966342111, 30 - CONST_BITS) ; FIX(0.899976223)
  45. F_1_175 equ DESCALE(1262586813, 30 - CONST_BITS) ; FIX(1.175875602)
  46. F_1_501 equ DESCALE(1612031267, 30 - CONST_BITS) ; FIX(1.501321110)
  47. F_1_847 equ DESCALE(1984016188, 30 - CONST_BITS) ; FIX(1.847759065)
  48. F_1_961 equ DESCALE(2106220350, 30 - CONST_BITS) ; FIX(1.961570560)
  49. F_2_053 equ DESCALE(2204520673, 30 - CONST_BITS) ; FIX(2.053119869)
  50. F_2_562 equ DESCALE(2751909506, 30 - CONST_BITS) ; FIX(2.562915447)
  51. F_3_072 equ DESCALE(3299298341, 30 - CONST_BITS) ; FIX(3.072711026)
  52. %endif
  53. ; --------------------------------------------------------------------------
  54. ; In-place 8x8x16-bit matrix transpose using AVX2 instructions
  55. ; %1-%4: Input/output registers
  56. ; %5-%8: Temp registers
  57. %macro DOTRANSPOSE 8
  58. ; %1=(00 01 02 03 04 05 06 07 40 41 42 43 44 45 46 47)
  59. ; %2=(10 11 12 13 14 15 16 17 50 51 52 53 54 55 56 57)
  60. ; %3=(20 21 22 23 24 25 26 27 60 61 62 63 64 65 66 67)
  61. ; %4=(30 31 32 33 34 35 36 37 70 71 72 73 74 75 76 77)
  62. vpunpcklwd %5, %1, %2
  63. vpunpckhwd %6, %1, %2
  64. vpunpcklwd %7, %3, %4
  65. vpunpckhwd %8, %3, %4
  66. ; transpose coefficients(phase 1)
  67. ; %5=(00 10 01 11 02 12 03 13 40 50 41 51 42 52 43 53)
  68. ; %6=(04 14 05 15 06 16 07 17 44 54 45 55 46 56 47 57)
  69. ; %7=(20 30 21 31 22 32 23 33 60 70 61 71 62 72 63 73)
  70. ; %8=(24 34 25 35 26 36 27 37 64 74 65 75 66 76 67 77)
  71. vpunpckldq %1, %5, %7
  72. vpunpckhdq %2, %5, %7
  73. vpunpckldq %3, %6, %8
  74. vpunpckhdq %4, %6, %8
  75. ; transpose coefficients(phase 2)
  76. ; %1=(00 10 20 30 01 11 21 31 40 50 60 70 41 51 61 71)
  77. ; %2=(02 12 22 32 03 13 23 33 42 52 62 72 43 53 63 73)
  78. ; %3=(04 14 24 34 05 15 25 35 44 54 64 74 45 55 65 75)
  79. ; %4=(06 16 26 36 07 17 27 37 46 56 66 76 47 57 67 77)
  80. vpermq %1, %1, 0x8D
  81. vpermq %2, %2, 0x8D
  82. vpermq %3, %3, 0xD8
  83. vpermq %4, %4, 0xD8
  84. ; transpose coefficients(phase 3)
  85. ; %1=(01 11 21 31 41 51 61 71 00 10 20 30 40 50 60 70)
  86. ; %2=(03 13 23 33 43 53 63 73 02 12 22 32 42 52 62 72)
  87. ; %3=(04 14 24 34 44 54 64 74 05 15 25 35 45 55 65 75)
  88. ; %4=(06 16 26 36 46 56 66 76 07 17 27 37 47 57 67 77)
  89. %endmacro
  90. ; --------------------------------------------------------------------------
  91. ; In-place 8x8x16-bit accurate integer forward DCT using AVX2 instructions
  92. ; %1-%4: Input/output registers
  93. ; %5-%8: Temp registers
  94. ; %9: Pass (1 or 2)
  95. %macro DODCT 9
  96. vpsubw %5, %1, %4 ; %5=data1_0-data6_7=tmp6_7
  97. vpaddw %6, %1, %4 ; %6=data1_0+data6_7=tmp1_0
  98. vpaddw %7, %2, %3 ; %7=data3_2+data4_5=tmp3_2
  99. vpsubw %8, %2, %3 ; %8=data3_2-data4_5=tmp4_5
  100. ; -- Even part
  101. vperm2i128 %6, %6, %6, 0x01 ; %6=tmp0_1
  102. vpaddw %1, %6, %7 ; %1=tmp0_1+tmp3_2=tmp10_11
  103. vpsubw %6, %6, %7 ; %6=tmp0_1-tmp3_2=tmp13_12
  104. vperm2i128 %7, %1, %1, 0x01 ; %7=tmp11_10
  105. vpsignw %1, %1, [rel PW_1_NEG1] ; %1=tmp10_neg11
  106. vpaddw %7, %7, %1 ; %7=(tmp10+tmp11)_(tmp10-tmp11)
  107. %if %9 == 1
  108. vpsllw %1, %7, PASS1_BITS ; %1=data0_4
  109. %else
  110. vpaddw %7, %7, [rel PW_DESCALE_P2X]
  111. vpsraw %1, %7, PASS1_BITS ; %1=data0_4
  112. %endif
  113. ; (Original)
  114. ; z1 = (tmp12 + tmp13) * 0.541196100;
  115. ; data2 = z1 + tmp13 * 0.765366865;
  116. ; data6 = z1 + tmp12 * -1.847759065;
  117. ;
  118. ; (This implementation)
  119. ; data2 = tmp13 * (0.541196100 + 0.765366865) + tmp12 * 0.541196100;
  120. ; data6 = tmp13 * 0.541196100 + tmp12 * (0.541196100 - 1.847759065);
  121. vperm2i128 %7, %6, %6, 0x01 ; %7=tmp12_13
  122. vpunpcklwd %2, %6, %7
  123. vpunpckhwd %6, %6, %7
  124. vpmaddwd %2, %2, [rel PW_F130_F054_MF130_F054] ; %2=data2_6L
  125. vpmaddwd %6, %6, [rel PW_F130_F054_MF130_F054] ; %6=data2_6H
  126. vpaddd %2, %2, [rel PD_DESCALE_P %+ %9]
  127. vpaddd %6, %6, [rel PD_DESCALE_P %+ %9]
  128. vpsrad %2, %2, DESCALE_P %+ %9
  129. vpsrad %6, %6, DESCALE_P %+ %9
  130. vpackssdw %3, %2, %6 ; %6=data2_6
  131. ; -- Odd part
  132. vpaddw %7, %8, %5 ; %7=tmp4_5+tmp6_7=z3_4
  133. ; (Original)
  134. ; z5 = (z3 + z4) * 1.175875602;
  135. ; z3 = z3 * -1.961570560; z4 = z4 * -0.390180644;
  136. ; z3 += z5; z4 += z5;
  137. ;
  138. ; (This implementation)
  139. ; z3 = z3 * (1.175875602 - 1.961570560) + z4 * 1.175875602;
  140. ; z4 = z3 * 1.175875602 + z4 * (1.175875602 - 0.390180644);
  141. vperm2i128 %2, %7, %7, 0x01 ; %2=z4_3
  142. vpunpcklwd %6, %7, %2
  143. vpunpckhwd %7, %7, %2
  144. vpmaddwd %6, %6, [rel PW_MF078_F117_F078_F117] ; %6=z3_4L
  145. vpmaddwd %7, %7, [rel PW_MF078_F117_F078_F117] ; %7=z3_4H
  146. ; (Original)
  147. ; z1 = tmp4 + tmp7; z2 = tmp5 + tmp6;
  148. ; tmp4 = tmp4 * 0.298631336; tmp5 = tmp5 * 2.053119869;
  149. ; tmp6 = tmp6 * 3.072711026; tmp7 = tmp7 * 1.501321110;
  150. ; z1 = z1 * -0.899976223; z2 = z2 * -2.562915447;
  151. ; data7 = tmp4 + z1 + z3; data5 = tmp5 + z2 + z4;
  152. ; data3 = tmp6 + z2 + z3; data1 = tmp7 + z1 + z4;
  153. ;
  154. ; (This implementation)
  155. ; tmp4 = tmp4 * (0.298631336 - 0.899976223) + tmp7 * -0.899976223;
  156. ; tmp5 = tmp5 * (2.053119869 - 2.562915447) + tmp6 * -2.562915447;
  157. ; tmp6 = tmp5 * -2.562915447 + tmp6 * (3.072711026 - 2.562915447);
  158. ; tmp7 = tmp4 * -0.899976223 + tmp7 * (1.501321110 - 0.899976223);
  159. ; data7 = tmp4 + z3; data5 = tmp5 + z4;
  160. ; data3 = tmp6 + z3; data1 = tmp7 + z4;
  161. vperm2i128 %4, %5, %5, 0x01 ; %4=tmp7_6
  162. vpunpcklwd %2, %8, %4
  163. vpunpckhwd %4, %8, %4
  164. vpmaddwd %2, %2, [rel PW_MF060_MF089_MF050_MF256] ; %2=tmp4_5L
  165. vpmaddwd %4, %4, [rel PW_MF060_MF089_MF050_MF256] ; %4=tmp4_5H
  166. vpaddd %2, %2, %6 ; %2=data7_5L
  167. vpaddd %4, %4, %7 ; %4=data7_5H
  168. vpaddd %2, %2, [rel PD_DESCALE_P %+ %9]
  169. vpaddd %4, %4, [rel PD_DESCALE_P %+ %9]
  170. vpsrad %2, %2, DESCALE_P %+ %9
  171. vpsrad %4, %4, DESCALE_P %+ %9
  172. vpackssdw %4, %2, %4 ; %4=data7_5
  173. vperm2i128 %2, %8, %8, 0x01 ; %2=tmp5_4
  174. vpunpcklwd %8, %5, %2
  175. vpunpckhwd %5, %5, %2
  176. vpmaddwd %8, %8, [rel PW_F050_MF256_F060_MF089] ; %8=tmp6_7L
  177. vpmaddwd %5, %5, [rel PW_F050_MF256_F060_MF089] ; %5=tmp6_7H
  178. vpaddd %8, %8, %6 ; %8=data3_1L
  179. vpaddd %5, %5, %7 ; %5=data3_1H
  180. vpaddd %8, %8, [rel PD_DESCALE_P %+ %9]
  181. vpaddd %5, %5, [rel PD_DESCALE_P %+ %9]
  182. vpsrad %8, %8, DESCALE_P %+ %9
  183. vpsrad %5, %5, DESCALE_P %+ %9
  184. vpackssdw %2, %8, %5 ; %2=data3_1
  185. %endmacro
  186. ; --------------------------------------------------------------------------
  187. SECTION SEG_CONST
  188. ALIGNZ 32
  189. GLOBAL_DATA(jconst_fdct_islow_avx2)
  190. EXTN(jconst_fdct_islow_avx2):
  191. PW_F130_F054_MF130_F054 times 4 dw (F_0_541 + F_0_765), F_0_541
  192. times 4 dw (F_0_541 - F_1_847), F_0_541
  193. PW_MF078_F117_F078_F117 times 4 dw (F_1_175 - F_1_961), F_1_175
  194. times 4 dw (F_1_175 - F_0_390), F_1_175
  195. PW_MF060_MF089_MF050_MF256 times 4 dw (F_0_298 - F_0_899), -F_0_899
  196. times 4 dw (F_2_053 - F_2_562), -F_2_562
  197. PW_F050_MF256_F060_MF089 times 4 dw (F_3_072 - F_2_562), -F_2_562
  198. times 4 dw (F_1_501 - F_0_899), -F_0_899
  199. PD_DESCALE_P1 times 8 dd 1 << (DESCALE_P1 - 1)
  200. PD_DESCALE_P2 times 8 dd 1 << (DESCALE_P2 - 1)
  201. PW_DESCALE_P2X times 16 dw 1 << (PASS1_BITS - 1)
  202. PW_1_NEG1 times 8 dw 1
  203. times 8 dw -1
  204. ALIGNZ 32
  205. ; --------------------------------------------------------------------------
  206. SECTION SEG_TEXT
  207. BITS 64
  208. ;
  209. ; Perform the forward DCT on one block of samples.
  210. ;
  211. ; GLOBAL(void)
  212. ; jsimd_fdct_islow_avx2(DCTELEM *data)
  213. ;
  214. ; r10 = DCTELEM *data
  215. align 32
  216. GLOBAL_FUNCTION(jsimd_fdct_islow_avx2)
  217. EXTN(jsimd_fdct_islow_avx2):
  218. ENDBR64
  219. push rbp
  220. mov rbp, rsp
  221. COLLECT_ARGS 1
  222. ; ---- Pass 1: process rows.
  223. vmovdqu ymm4, YMMWORD [YMMBLOCK(0,0,r10,SIZEOF_DCTELEM)]
  224. vmovdqu ymm5, YMMWORD [YMMBLOCK(2,0,r10,SIZEOF_DCTELEM)]
  225. vmovdqu ymm6, YMMWORD [YMMBLOCK(4,0,r10,SIZEOF_DCTELEM)]
  226. vmovdqu ymm7, YMMWORD [YMMBLOCK(6,0,r10,SIZEOF_DCTELEM)]
  227. ; ymm4=(00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17)
  228. ; ymm5=(20 21 22 23 24 25 26 27 30 31 32 33 34 35 36 37)
  229. ; ymm6=(40 41 42 43 44 45 46 47 50 51 52 53 54 55 56 57)
  230. ; ymm7=(60 61 62 63 64 65 66 67 70 71 72 73 74 75 76 77)
  231. vperm2i128 ymm0, ymm4, ymm6, 0x20
  232. vperm2i128 ymm1, ymm4, ymm6, 0x31
  233. vperm2i128 ymm2, ymm5, ymm7, 0x20
  234. vperm2i128 ymm3, ymm5, ymm7, 0x31
  235. ; ymm0=(00 01 02 03 04 05 06 07 40 41 42 43 44 45 46 47)
  236. ; ymm1=(10 11 12 13 14 15 16 17 50 51 52 53 54 55 56 57)
  237. ; ymm2=(20 21 22 23 24 25 26 27 60 61 62 63 64 65 66 67)
  238. ; ymm3=(30 31 32 33 34 35 36 37 70 71 72 73 74 75 76 77)
  239. DOTRANSPOSE ymm0, ymm1, ymm2, ymm3, ymm4, ymm5, ymm6, ymm7
  240. DODCT ymm0, ymm1, ymm2, ymm3, ymm4, ymm5, ymm6, ymm7, 1
  241. ; ymm0=data0_4, ymm1=data3_1, ymm2=data2_6, ymm3=data7_5
  242. ; ---- Pass 2: process columns.
  243. vperm2i128 ymm4, ymm1, ymm3, 0x20 ; ymm4=data3_7
  244. vperm2i128 ymm1, ymm1, ymm3, 0x31 ; ymm1=data1_5
  245. DOTRANSPOSE ymm0, ymm1, ymm2, ymm4, ymm3, ymm5, ymm6, ymm7
  246. DODCT ymm0, ymm1, ymm2, ymm4, ymm3, ymm5, ymm6, ymm7, 2
  247. ; ymm0=data0_4, ymm1=data3_1, ymm2=data2_6, ymm4=data7_5
  248. vperm2i128 ymm3, ymm0, ymm1, 0x30 ; ymm3=data0_1
  249. vperm2i128 ymm5, ymm2, ymm1, 0x20 ; ymm5=data2_3
  250. vperm2i128 ymm6, ymm0, ymm4, 0x31 ; ymm6=data4_5
  251. vperm2i128 ymm7, ymm2, ymm4, 0x21 ; ymm7=data6_7
  252. vmovdqu YMMWORD [YMMBLOCK(0,0,r10,SIZEOF_DCTELEM)], ymm3
  253. vmovdqu YMMWORD [YMMBLOCK(2,0,r10,SIZEOF_DCTELEM)], ymm5
  254. vmovdqu YMMWORD [YMMBLOCK(4,0,r10,SIZEOF_DCTELEM)], ymm6
  255. vmovdqu YMMWORD [YMMBLOCK(6,0,r10,SIZEOF_DCTELEM)], ymm7
  256. vzeroupper
  257. UNCOLLECT_ARGS 1
  258. pop rbp
  259. ret
  260. ; For some reason, the OS X linker does not honor the request to align the
  261. ; segment unless we do this.
  262. align 32